ASUS Z87-A Intel Z87 Haswell motherboard Review with Intel Core i7-4770 processor

THE BIOS

The BIOS has a comprehensive set of options for you to tune up your system. For users who just want to run it at default, you can use XMP profiles detected from the DIMMs. Of course, fine tuning requires much effort. If you just want a straightforward overclocked system, you can use the TPU to do it for you.

The DRAM, Cache speed, CPU graphics speed and DMI/PEG Clock are all dependent on the BCLK. For K series processors, the BCLK can be set to run higher than the usual 105MHz. This is because when BCLK goes higher than 125MHz, the DMI clock goes back to 100MHz. The DMI clk will be at 100MHz as it runs at a ratio of the BCLK.

In the BIOS, you also sync all cores to the core ratio limit., change the min and max Cache ratio and DRAM frequency the RAM runs at.

Below is a run through of all the options available in the BIOS.

Adjustable Voltage Range:
Options
Available Options
CPU Core Voltage Override 0.001~1.920, under 0.001V increment
CPU Cache Voltage Override 0.001~1.920, under 0.001V increment
CPU Graphics Voltage Override 0.001~1.920, under 0.001V increment
CPU Core Voltage Offset -0.999~0.999, under 0.001V increment
CPU Cache Voltage Offset -0.999~0.999, under 0.001V increment
CPU Graphics Voltage Offset -0.999~0.999, under 0.001V increment
Additional Turbo Mode CPU Core Voltage 0.001~1.920, under 0.001V increment
Additional Turbo Mode CPU Cache Voltage 0.001~1.920, under 0.001V increment
Additional Turbo Mode CPU Graphics Voltage 0.001~1.920, under 0.001V increment
CPU System Agent Voltage Offset -0.999~0.999, under 0.001V increment
CPU Analog I/O Voltage Offset -0.999~0.999, under 0.001V increment
CPU Digital I/O Voltage Offset -0.999~0.999, under 0.001V increment
CPU Input Voltage
0.800~2.700V(Extreme OV Disabled) or
0.800~3.040V(Extreme OV Enabled) under 0.01V
increment
SVID Voltage Override 0.001~2.440V under 0.01V increment
DRAM Voltage 1.20000~1.92000V under 0.01000V increment
PCH VLX Voltage 1.20000~2.00000V under 0.01250V increment
PCH Voltage 0.70000~1.50000V under 0.01250V increment
DRAM CTRL REF Voltage 0.39500~0.63000V under 0.00500V increment
DRAM DATA REF Voltage on Channel A 0.39500~0.63000V under 0.00500V increment
DRAM DATA REF Voltage on Channel B 0.39500~0.63000V under 0.00500V increment
Clock Crossing Vboot 0.10000~1.90000V under 0.00625V increment
Clock Crossing Reset Voltage 0.10000~1.90000V under 0.00625V increment
Clock Crossing Voltage 0.10000~1.90000V under 0.00625V increment
Adjustable Frequency Range:
Options
Available Options
CPU Strap 100MHz / 125MHz / 167MHz / 250MHz
BCLK Frequency 80.0~300.0, under 0.1MHz increment
1/2/3/4-Core Ratio Limit Lowest Turbo Ratio ~ 80, under 1x interval
Min CPU Cache Ratio 8~80, under 1x interval
Max CPU Cache Ratio 8~80, under 1x interval
CPU bus speed : DRAM speed ratio mode 100:133 / 100:100
Memory Frequency Vary depending on the BCLK used.
CPU Graphics Max. Ratio 25~60, under 1x interval
DRAM CAS# Latency 1~31, under 1x interval
DRAM RAS# to CAS# Delay 1~31, under 1x interval
DRAM RAS# PRE Time 1~31, under 1x interval
DRAM RAS# ACT Time 1~63, under 1x interval
DRAM Command Mode 1~3, under 1x interval
DRAM RAS# to RAS# Delay 1~15, under 1x interval
DRAM REF Cycle Time 1~511, under 1x interval
DRAM Refresh Interval 1~65535, under 1x interval
DRAM WRITE Recovery Time 1~16, under 1x interval
DRAM READ to PRE Time 1~15, under 1x interval
DRAM FOUR ACT WIN Time 1~255, under 1x interval
DRAM WRITE to READ Delay 1~15, under 1x interval
DRAM CKE Minimum pulse width 1~15, under 1x interval
DRAM CAS# Write Latency 1~31, under 1x interval
tRDRD 1~7, under 1x interval
tRDRD_dr 1~15, under 1x interval
tRDRD_dd 1~15, under 1x interval
tWRRD 1~63, under 1x interval
tWRRD_dr 1~15, under 1x interval
tWRRD_dd 1~15, under 1x interval
tWRWR 1~7, under 1x interval
tWRWR_dr 1~15, under 1x interval
tWRWR_dd 1~15, under 1x interval
Dec_WRD 0~1, under 1x interval
tRDWR 1~31, under 1x interval
tRDWR_dr 1~31, under 1x interval
tRDWR_dd 1~31, under 1x interval
DRAM CLK Period 1~14, under 1x interval
DRAM RTL Initial Value 1~63, under 1x interval
DRAM RTL (CHA_R0D0) 1~63, under 1x interval
DRAM RTL (CHA_R0D1) 1~63, under 1x interval
DRAM RTL (CHA_R1D0) 1~63, under 1x interval
DRAM RTL (CHA_R1D1) 1~63, under 1x interval
DRAM RTL (CHB_R0D0) 1~63, under 1x interval
DRAM RTL (CHB_R0D1) 1~63, under 1x interval
DRAM RTL (CHB_R1D0) 1~63, under 1x interval
DRAM RTL (CHB_R1D1) 1~63, under 1x interval
DRAM IO-L (CHA_R0D0) 1~15, under 1x interval
DRAM IO-L (CHA_R0D1) 1~15, under 1x interval
DRAM IO-L (CHA_R1D0) 1~15, under 1x interval
DRAM IO-L (CHA_R1D1) 1~15, under 1x interval
DRAM IO-L (CHB_R0D0) 1~15, under 1x interval
DRAM IO-L (CHB_R0D1) 1~15, under 1x interval
DRAM IO-L (CHB_R1D0) 1~15, under 1x interval
DRAM IO-L (CHB_R1D1) 1~15, under 1x interval

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